CIMdata PLM Industry Summary Online Archive
21 January 2008
Product News
STARC Releases 'Pride' Reference Design Flow Using Cadence Low-Power and DFM Solutions
Cadence Design Systems, Inc. announced that Japan's Semiconductor Technology Academic Research Center (STARC) has released its next-generation ultra low-power "PRIDE" reference flow V1.5, incorporating the Common Power Format (CPF)-based Cadence Low-Power Solution. This reference flow also includes key litho-aware manufacturing (DFM) technologies from Cadence®. The release follows months of rigorous development and testing by STARC engineers using multiple test designs. This reference flow is expected to provide significant power savings, yield enhancement and time-to-market advantages for STARC members producing high-volume consumer, communications and mobile electronic devices on 65- and 45-nanometer processes.
"The STARC PRIDE V1.5 Flow incorporates numerous requirements from our member companies for an advanced ultra low-power solution and an optimized DFM methodology," said Nobuyuki Nishiguchi, vice president and general manager of STARC. "The CPF-based Cadence Low-Power Solution delivers a fully automated flow for the architectural exploration, design, verification and implementation of low-power SoCs. The PRIDE V1.5 Flow also takes advantage of Cadence's DFM technologies to reduce overall design time and increase production yields for high-volume designs."
Targeting 65- and 45-nanometer designs, the PRIDE V1.5 Flow incorporates the CPF-based Cadence low-power design solution supported by Cadence's Incisive® and Encounter® platforms to provide an automated and holistic low-power design flow from RTL design through GDS II tape-out. PRIDE V1.5 enables front-end designers to explore physical prototyping with different CPF files and a single golden RTL, allowing low-power architecture optimization. In pilot designs, using the CPF-based Cadence Low-Power Solution STARC has confirmed 3X improvement in design time for architectural exploration to floorplan for low-power chips that employ advanced power management techniques such as multi-supply voltages and power shut-off. In addition to design productivity improvements, these techniques enabled up to 40% power reduction in the pilot designs.
Cadence's DFM technologies include Model-based Verification, Litho Physical Analyzer, Litho Electrical Analyzer, CMP Predictor and Chip Optimizer technologies, which allow designers to analyze, optimize and correct potential yield limiters early in the design process, including physical and electrical effects produced during lithography. Cadence's comprehensive model-based manufacturability solutions provide analysis of IP and full-chip designs for random and systematic manufacturing variations to prevent any catastrophic or parametric failures before tape-out. This enables "What You Design Is What You Get" (WYDIWYG) design for manufacturability to designers using advanced-node technologies.
"STARC and Cadence worked closely to implement and validate this DFM-aware low-power design flow and deliver an optimized design methodology to our customers," said Chi-Ping Hsu, corporate vice president of IC Digital and the Power Forward Initiative at Cadence. "This CPF-based reference flow provides STARC members with the industry's only end-to-end, integrated low-power solution incorporating an advanced DFM methodology."
CPF is a Si2 standard format for specifying power-saving techniques early in the design process—enabling sharing and reuse of low-power intelligence throughout the design process. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Si2-standard Common Power Format. This low-power solution has been available to designers for more than a year and has been used in more than 50 customer tapeouts worldwide.
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