CIMdata PLM Industry Summary Online Archive
8 February 2007
Implementation Investments
Mplicity Standardizes on Synopsys Formality Solution for Verification of Multi-Core Design Flow
Synopsys, Inc. announced that Mplicity, a leader in multi-core design implementation, has standardized on the Synopsys Formality® equivalence checking solution and its retiming verification methodology for customers of Mplicity's CoreUpGrade offering. The Formality solution extends the reach of equivalence checking technology to provide a comprehensive verification offering that addresses complex design optimizations.
"Mplicity's "CoreUpGrade" product transforms a given single-processor core into an enriched multi-core, boosting silicon performance while reducing chip size and power consumption," said Eran Dagan, chief technology officer at Mplicity. "Register retiming is a significant part of the CoreUpGrade process and Synopsys' Formality verification technology excelled in its ability to verify this and other optimizations for our customers."
The Synopsys retiming verification methodology uses enhanced solver technologies to account for combinational changes that may have occurred during implementation. This methodology extends the reach of verification into spaces previously thought unverifiable by equivalence checking technology. Synopsys collaborated with Mplicity to ensure that the multi-core verification flow records the retiming and other data so that designers can verify all aspects of their multi-core design implementation flow.
"There has long been a gap between the level of design optimization achieved during implementation and what equivalence checking technology could readily verify," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "The Formality-guided methodology safely closes this gap, allowing for significant improvements in design quality without sacrificing verifiability."
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