CIMdata PLM Industry Summary Online Archive

6 February 2007

Company News

Chip Estimate Announces Prime IP Partner Program

Chip Estimate Corporation announced that it has launched the Prime IP Partner Program to enable centralized access to information about intellectual property portfolios of industry-leading IP (Intellectual Property) providers. Thirty-six IP providers have joined this program since the July launch of the ChipEstimate.com portal, which offers comprehensive chip planning capabilities to the electronics and semiconductor community. The Prime IP Partner Program combined with other IP vendor partners represent over 200 companies whose IP can be searched for and considered in chip estimations though the website.

"Launching this elevated IP partner program addresses the needs of Chip Estimate's growing community of users to further simplify and accelerate the process of finding the best IP for their next chip project," commented Casey Jones, VP Marketing for Chip Estimate. "We are pleased to be launching this program with such a stellar list of IP partners."

Prime IP Partners offer the ChipEstimate.com community an elevated level of service and information regarding their IP offerings, including IP status-in-silicon, up-to-date data on their latest products, and news related to their latest IP releases. In addition, these select partners deliver streamlined service through a tight connection with ChipEstimate.com community. Users are now able to use the website as a central portal for finding the latest semiconductor IP information, contacting leading IP suppliers, and can estimate their chip die size, power, leakage and cost with selected IP. Over 10,000 designers rely on ChipEstimate.com at the inception of design planning to find IP and develop chip plans, consider IP options in the context of their chip specifications, and perform rapid architectural what-if analysis to ultimately reduce chip cost and speed time to market.

Prime IP Partners include ARC, IPextreme, Mentor Graphics and Virage Logic. A complete list can be seen at http://www.chipestimate.com/vendorlist.php .

Prime IP Partners Speak Out

"ARC is pleased to join this new program, and through it to deliver greater visibility into the configurable processor technology solutions we offer to meet the needs of the advanced SoC design community," commented Karl Auker, Director, Strategic Alliances at ARC.

"IPextreme has joined the Chip Estimate community as the relationship enhances the visibility of the IP we offer, and allows chip planners to explore our IP in the context of their chip regardless of what EDA tools they ultimately will use," commented Trent Poltronetti, IPextreme VP of Marketing.

"The Prime IP Partner program gives the design planning community an easy way to explore Mentor IP in the context of their specific designs," stated Bill Martin, General Manager, Mentor Graphics Intellectual Property Division. "Our participation with Chip Estimate will help meet the needs of today's designers with Mentor's silicon-proven, ready-to-use standards-based IP solutions."

"Virage Logic is always looking for ways to streamline our customers' IP exploration and selection process," commented Tom Griffin, Senior Director, Business Development at Virage Logic. "ChipEstimate.com adds the ability to combine Virage Logic memories with foundation IP and predict chip size, power and leakage."

About Chip Estimate Corporation's Products

The ChipEstimate.com website includes datasheets for all IP partners' portfolios, and IP can be searched for by vendor or functional type using a rank-by-relevance search engine. Selected IP can be added to an IP list that can be imported into a copy of Chip Estimate's system, InCyteTM for exploration and consideration in a chip design context.

InCyte performs estimations of chip die size, power, leakage, yield and cost and allows for rapid "what if" analysis at the architectural stage in the design flow. The system is also used by leading semiconductor companies to refine chip size, power and cost estimates throughout chip implementation flows.

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