CIMdata PLM Industry Summary Online Archive
30 January 2007
Implementation Investments
Cadence Enables Silicon & Software Systems to Design Record-Breaking Low-Power Chip
Cadence Design Systems, Inc. announced that Silicon & Software Systems Ltd. ( S3 ) achieved record-breaking production success for a chip designed at S3's facilities, using the company's nanoflowLP® low-power system-on-chip (SoC) design flow based on the Cadence® Low-Power Solution.
S3 used a range of low-power design techniques such as multi-Vt libraries, power islands, power estimation and low-power verification for this chip, intended for mobile audio applications. The chip booted correctly the first time in a portable computer application within 24 hours of wafers arriving from the foundry and consumed only 85 percent power of the original power budget target set by the customer.
The Cadence Low-Power Solution integrates design, verification, and implementation technology with the Si2 Common Power Format (CPF), a standardized format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution to IC engineers. By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, greatly reduces power-related chip failure, and provides power predictability early in the design process. This holistic approach to addressing the low-power challenge is necessary for managing power consumption in 90-nanometer and 65-nanometer designs.
"With the Cadence Low-Power Solution we were able to optimize our nanoflowLP and leverage our strong engineering expertise and experience," said Dermot Barry, general manager, System IC Business Unit, S3. "As a result, our customers achieve right-first-time silicon and reduced time to revenue. With the latest low-power optimized flow from Cadence we can now meet the high expectations of our customers."
"We applaud S3's ability to deliver another customer success based on our extensive low-power flow-development partnership. The exciting technology advancement by the Cadence Low-Power Solution, based on the Common Power Format, brings a new level of automation to the ever challenging low-power designs at deep sub-micron nodes," said Dr. Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. "S3's ability to incorporate the latest low-power techniques and deliver fast turn-around times means that lowest cost SoCs can be achieved with minimal risk or compromise on performance."
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