CIMdata PLM Industry Summary Online Archive
5 December 2007
Product News
Cadence and ARM Deliver Reference Methodologies for Multicore and Low-Power Devices
Cadence Design Systems, Inc. and ARM announced the availability of two new implementation reference methodologies jointly developed by the companies, one for the ARM11T MPCoreT multicore processor and the other for low-power implementation of the ARM1176JZF-ST processor, which incorporates ARM® Intelligent Energy Manager (IEMT) technology. These Cadence reference methodologies for the two ARM processors are the result of close collaboration between the two companies, and provide enhanced design solutions to mutual customers designing multicore, low-power devices.
"With the Cadence Low-Power Solution, which includes Encounter RTL Compiler and SoC Encounter GXL, we have been able to exceed performance goals for our ARM processor-based ASIC design efforts," said Ying F. Chang, engineering director, Custom SOC Solutions Engineering, NEC Electronics America. "We applaud the collaboration between ARM and Cadence to deliver flows that will speed and simplify the delivery of lower-power ARM processors."
The ARM11 MPCore multicore processor was the first to feature ARM MPCore multiprocessing technology, which provides a scalable solution for both performance and power management that can address the requirements of multiple designs.
"The reference methodology for the ARM11 MPCore multicore processor provides a high-performance reference flow that offers predictable, low-risk implementation of multiprocessor configurations," said Keith Clarke, vice president of technical marketing at ARM. "Both the ARM11 MPCore processor and low-power ARM1176JZF-S processor flows have been pre-validated with ARM Artisan® Physical IP in order to optimize the implementation of ARM synthesizable processor IP."
The low-power reference methodology for the ARM1176JZF-S processor provides enhanced features required to support IEM technology, which has been shown to reduce CPU energy consumption by more than 60 percent, and supports the Dynamic Voltage and Frequency Scaling (DVFS) hardware technique that IEM technology exploits.
The reference methodologies comprehend the Common Power Format (CPF), which enables the up-front specification of power domains, power modes, level shifting and isolation rules to automate advanced low-power design techniques. The methodologies leverage a wide range of products of the Cadence® Low-Power Solution, including the Cadence SoC EncounterT RTL-to-GDSII system, Encounter® RTL Compiler with global synthesis, Encounter Conformal® Low Power, and VoltageStorm® power rail analysis.
"These jointly developed reference methodologies offer significant benefits in multiprocessing and power consumption for customers designing the next-generation consumer devices which require performance and superior power management," said Mike McAweeney, vice president, Product Marketing at Cadence . "Use of the reference methodologies by engineering teams helps reduce time to tapeout of customized designs, thereby gaining considerable time-to-market and cost benefits."
ARM and Cadence, a member of the ARM Connected Community, will leverage their extensive experience gained in developing these advanced flows for low-power and multiprocessing applications in the development of new reference methodologies for the latest ARM processors, the CortexT A9 processor and the ARM Cortex-A9 MPCore multicore processor. These reference methodologies are planned to be available at the time of the production release of these new processors in the first half of 2008.
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