CIMdata PLM Industry Summary Online Archive
4 December 2007
Implementation Investments
Cadence Marks 100th Customer Adoption of Encounter Timing System
Cadence Design Systems, Inc. announced that the Cadence® Encounter® Timing System sign-off solution has been adopted and deployed by 100 customers since its launch just one year ago. Already in use by companies such as TSMC, Freescale Semiconductor and Faraday Technology Corp., Encounter Timing System plays an integral role in the design and development of leading-edge chips ranging from networking and telecommunications devices to microprocessors and graphics chips. Encounter Timing System is now being employed by customers 99 and 100, the innovative startups Luminary Micro and Element CXI.
Encounter Timing System is a complete and integrated electrical signoff environment, enabling faster optimization, debug and final verification of designs for timing, signal integrity, power and statistical analysis. Its innovative interface provides a common electrical view through every stage of the design flow, enabling significantly increased productivity and accelerated time to market while supporting a robust debug environment capable of providing rapid diagnosis of multi-dimensional and interdependent design-closure issues. Cadence Encounter Timing System is also an integral element of the Cadence SoC EncounterT RTL-to-GDSII system, where it helps to reconcile timing and improve the overall predictability, productivity and performance of the design.
"We have successfully taped out five industry-leading microcontroller chips using the signoff-driven implementation in the SoC Encounter system," said Dale Littwin, CAD manager at Luminary Micro. "We are impressed by the productivity improvements in signal integrity and global timing debug, as well as the unified environment. We have used the common timing engine in both the SoC Encounter system and Encounter Timing System for some time now and consider it a mature solution for signoff timing."
"We have successfully taped out our Elemental Computing Array (ECA-64) chip at 90 nanometers with Encounter Timing System," said Joseph Hassoun, director of Hardware Engineering, Element CXI. "The correlation to silicon and the fast run times achieved by using Encounter Timing System exceeded our expectations. We plan to continue using Encounter Timing System on our upcoming design tape-outs."
"It's great to see these innovative semiconductor companies joining the ranks of IC providers and design houses that have adopted Encounter Timing System for their leading-edge designs. Achieving 100 customer adoptions so quickly is a strong validation of the value and quality of Encounter Timing System," said David Desharnais, group director of IC Digital Marketing at Cadence. "In addition, new features such as statistical analysis will enable our customers to unlock the true potential of smaller process geometries."
A ubiquitous technology within the Cadence Digital Implementation solution and a component of the Cadence Logic Design Team Solution, Encounter Timing System is available in L, XL and GXL offerings.
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