CIMdata PLM Industry Summary Online Archive
13 November 2007
Product News
Altera and Synopsys Collaborate to Make Nios II Processor Core Available for ASIC Designs
Altera Corporation and Synopsys, Inc ., announced that Altera's popular Nios® II processor core will be available for licensing through Synopsys' DesignWare® Star IP Program. Expanding on Altera's existing FPGA and HardCopy® structured ASIC product deployment options, this new offering enables Nios II users to migrate their designs to standard cell ASICs. The Nios II processor core is the most widely used FPGA-based processor, with more than 5,000 electronics manufacturers-including the world's top electronics OEMs-in the customer base.
"We have been deploying products based on the Nios II processor core in ASIC forms for several years," said Eric Lu, chairman of Lionic Corporation. "We welcome the new offering from Altera and Synopsys, because the combination of an ASIC-optimized Nios II processor core, all the supporting DesignWare IP, and the best-in-class design and simulation tools from Synopsys will help ensure quality and the shortest time to market."
"We have used Altera's Nios II processor core in a number of projects targeting FPGA devices," said Karlheinz Ronge, head of department, IC design digital systems at Fraunhofer Institute Integrated Circuits, Erlangen, Germany. "Having an option to use the Nios II processor core for standard cell ASICs through Synopsys, in addition to FPGAs and structured ASICs, will allow us to broaden our usage of this powerful and flexible processor core for high-volume applications."
The DesignWare Star IP program provides designers access to high-performance, high-value processor and DSP cores developed by leading Star IP providers. Utilizing its core competencies in design-for-reuse, intellectual property (IP) packaging methodologies and design flows, Synopsys will provide a configurable, fully synthesizable version of the Nios II processor core optimized for ASIC implementation. Designers will be able to use the core in the foundry and process technology of their choice. By combining this reusable core with Synopsys' leading portfolio of tools, support, design services and additional key system-on-chip IP building blocks, Synopsys offers designers a robust solution for realizing their Nios II processor-based ASICs and ASSPs.
"As the Nios II processor core is the most widely used FPGA-based processor, we continue to see a growing demand from our customers to expand their silicon deployment options," said Chris Balough, Altera's director of software and embedded marketing. "The partnering of our versatile Nios II processor core with Synopsys' strengths in ASIC IP and design makes for a strong solution to meet our customers' needs."
"The collaboration between A ltera and Synopsys to include the Nios II processor core in the DesignWare Star IP program extends availability of the core to a broad set of ASIC customers and applications," said John Koeter, senior director of marketing for IP and services at Synopsys. "Designers can now take advantage of the Nios II configurability and scalability in their industry-standard ASIC design flow and turn to Synopsys as a single source for their ASIC IP, support and services needs."
Availability
The synthesizable version of the Nios II processor core is expected to be available from Synopsys in the first quarter of 2008.
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