CIMdata PLM Industry Summary Online Archive
13 November 2007
Implementation Investments
Faraday Chooses Cadence Voltagestorm for Advanced 65nm Low-power Signoff
Cadence Design Systems, Inc. and Faraday Technology Corporation announced that Faraday has adopted the Cadence® VoltageStorm® power analysis technology for low-power signoff and to support Faraday's low-power designs. Faraday uses VoltageStorm's static and dynamic power analysis to validate its advanced low-power design methodology, which includes power gating, de-coupling capacitance optimization, and multi-supply, multi-voltage (MSMV) scaling.
Faraday had an existing power analysis solution which was successfully employed down to 90 nanometers. However, recognizing the new technical challenges of low-power signoff at 65 nanometers and below, Faraday engaged in an extensive evaluation of all commercially available power analysis and IR drop solutions on the market. Following this comprehensive evaluation, VoltageStorm power analysis was selected as the only solution available to accurately validate Faraday's complex low-power designs. In addition, the integration of VoltageStorm analysis and Cadence SoC EncounterT RTL-to-GDSII system-Faraday's selected design implementation solution-provided a superior solution capable of optimizing power switches and de-coupling capacitance during implementation, which proved to be of high value to Faraday.
"We were really concerned with the accuracy of power analysis for our advanced low-power designs at 65 nanometers, and the accuracy of power analysis for our advanced low-power designs at 65 nanometers," said C. J. Hsieh, associate vice president of SoC Development and Service at Faraday. "Following our rigorous evaluation, VoltageStorm analysis clearly demonstrated that it has the functionality, accuracy, capacity and performance to meet our future production needs. The ability to execute VoltageStorm analysis directly from SoC Encounter system has significantly increased ease of use for our back-end design engineers," he added.
A key component of the Cadence Low-Power Solution and an integral part of the Encounter® digital IC design platform, VoltageStorm's static and dynamic power analysis validates for full-chip IR drop and power rail electromigration. Automatic optimization of de-coupling capacitance and power switches is enabled via tight integration with the SoC Encounter system.
"At 65 nanometers and below, it is especially critical that low-power design teams properly optimize de-coupling capacitances to tame dynamic IR drop transients, and reduce the number of power switches required to turn off blocks of logic," said Chi-Ping Hsu, vice president of Cadence's digital implementation group. "The integration of SoC Encounter system and VoltageStorm power analysis provides completely automated optimization and replaces engineering guesswork with signoff-accurate analysis during the design flow, greatly increasing quality of silicon (QoS) and tapeout confidence."
VoltageStorm power analysis allows low-power design teams to minimize IR drop, avoid electromigration, maximize the efficiency of added de-coupling capacitance and power switches, and helps ensure a robust power network design that will not be a cause of silicon failure.
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