CIMdata PLM Industry Summary Online Archive

6 November 2007

Implementation Investments

Synopsys Selected to Develop 45-Nanometer USB PHY IP for IBM Foundry Process

Synopsys, Inc. announced an agreement with IBM to port the Synopsys DesignWare® USB 2.0 nanoPHY IP to the 45-nanometer (nm) Common PlatformT process. This agreement further strengthens the collaboration between the companies to provide USB PHY IP for IBM's leading process technologies, including 130-, 90- and 65-nm, all of which are silicon-proven, USB logo-certified and in volume production. Synopsys is the first IP provider to announce the development of a mixed-signal USB 2.0 PHY IP targeting this 45-nm process technology. The Synopsys DesignWare USB 2.0 nanoPHY IP will be designed with Common Platform technology design rules to provide GDSII compatibility between Common Platform technology manufacturers.

The IP is targeted for a broad range of high-volume, low-power mobile and consumer applications where the key requirements include minimal area and low power consumption. The DesignWare USB 2.0 nanoPHY addresses these key requirements by implementing an architecture that provides a highly effective combination of small area, low power consumption and low leakage. In addition, the DesignWare USB 2.0 nanoPHY IP has unique built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify the existing design. This feature enables designers to increase yield and minimize the cost of expensive silicon re-spins.

"High speed data connectivity IP is critical for customers using the latest process technologies," said Ken Torino, director of Foundry Products, IBM Global Engineering Solutions. "Based on the past proven successes with Synopsys' DesignWare IP implemented in the Common Platform 90- and 65-nanometer processes, it is natural to extend the relationship to the development of 45-nanometer USB PHY IP."

Availability

The 45-nm DesignWare USB 2.0 nanoPHY IP is scheduled for availability in the 1H08. The 65-nm version of the USB-IF-certified DesignWare USB 2.0 nanoPHY, as well as the synthesizable USB digital controllers, and verification IP are available today. Synopsys also offers PHYs, digital controllers, and verification IP for the PCI Express, SATA, and XAUI protocols in the Common Platform 65-nm process. More information about the DesignWare USB IP solution is available at http://www.synopsys.com/designware/usb_solutions.html .

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