CIMdata PLM Industry Summary Online Archive
31 October 2007
Product News
Zuken and Aldec Deliver New Design Solution: CADSTAR FPGA
As a result of the partnership between Zuken and Aldec , a brand new collaborative product for complete FPGA design and verification has been launched. CADSTAR FPGA combines Aldec's Active-HDL Lite verification tool and Zuken's desktop PCB design suite, CADSTAR, allowing engineers to perform mixed language simulation for vendor neutral FPGAs within the CADSTAR environment.
Synchronized Design Process
The relationship between the FPGA and PCB design processes is a primary area where synchronization can deliver opportunities for increased efficiency in the design process. CADSTAR FPGA technology is structured on integration of FPGA design within the PCB layout. The concurrent and collaborative process that this tool provides is made simple using an intuitive easy-to-use Design Flow Manager. This eliminates manual movement and back-annotation requirements, reducing time to market while increasing output of right-first-time designs.
Multi-vendor Support
CADSTAR FPGA combines Aldec's Active-HDL Lite design simulation environment and Zuken's desktop PCB design suite, CADSTAR. Engineers can perform comprehensive FPGA designs with complete support for technology from multiple FPGA vendors including Actel, Altera, Lattice, Quicklogic and Xilinx. It also performs mixed VHDL and Verilog simulation, strictly adhering to the latest IEEE language standards.
Easy to Use
CADSTAR FPGA provides one universal project manager that controls all design files for simulation, synthesis, place and route and pin assignment to the PCB. This integrated solution supports robust I/O synchronization between the FPGA device and the PCB, helping to optimize the routing pattern for high-density devices like BGAs.
More information
Aldec will host a CADSTAR FPGA web cast on November 8 - register at: http://www.aldec.com/avms/ This technical web-based methodology training will provide a comprehensive overview of the integration between CADSTAR and Active-HDL.
For more information: technical data sheets or evaluation software, please visit http://www.cadstarworld.com/FPGA/ or contact your local CADSTAR distributor.
The beta version of CADSTAR FPGA will be available from November 5 starting from $1000/€750 for a single language version.
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