CIMdata PLM Industry Summary Online Archive
23 October 2007
Implementation Investments
Cadence Encounter Test Helps Enable IBM To Deliver High-volume Chips
Cadence Design Systems, Inc . said that it has helped IBM deliver high-quality, high-volume chips for consumer devices by enabling the detection and correction of "small delay defects"-miniscule defects that are nearly invisible without sophisticated test programs that operate above the normal operating speed of the chip. Most recently, the Cadence Encounter® Test solution was able to help IBM meet its goals for quality and volume production of a high-performance custom chip based on IBM's Power ArchitectureT technology.
With consumer electronics taking advantage of more advanced semiconductor technology, the process to test, identify and remove defective parts from the supply chain has become more challenging. By today's standards, a show-stopping defect can be extremely small-a few atoms wide-resulting in timing delays as little as a tenth of a nanosecond-about the time it takes light to travel just a few inches.
The problem, of course, is that finding a defect in a super-small, super-dense and super-fast chip is a significant challenge. To address this problem today, IBM is working with Cadence Design Systems' Encounter Test group.
"The Cadence Encounter Test team has a capability called small delay defect detection," said Ron Martino, director of Power Architecture, IBM Global Engineering Solutions. "What this means is, they can detect a timing delay in a signal that is caused not by a broken wire, but by one that is merely a few atoms thinner than it is supposed to be. The difference in thickness creates a difference in resistivity, which delays the signal for a fraction of a nanosecond. In many high-performance, high volume applications, that's just too long."
Traditional test methodologies using test vectors can overlook such small delays, enabling test escapes that eventually manifest themselves as consumer product failures. Cadence Encounter Test avoids this problem through Encounter True-Time Test, which accelerates the speed of the device to reveal very small timing delays, much as running an automobile engine at a high RPM will reveal performance issues that would not show up at a lower speed.
"By using the Encounter True-Time Test capability, IBM was able to assure low defect rates for a superscalar chip design," said Sanjiv Taneja, vice president of Encounter Test R&D at Cadence. "This was important for IBM, it's important for their customer, but most of all, it's important for users of high-performance systems, because it demonstrates that there are ways to enable higher quality even as the semiconductor industry moves to smaller and more complex technologies."
The Cadence Encounter Test Solution will be demonstrated at the International Test Conference (ITC) 2007 at the Santa Clara Convention Center, October 23-26, 2007.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.