CIMdata PLM Industry Summary Online Archive
22 October 2007
Product News
Virage Logic Broadens Its Silicon Aware Intellectual Property (IP) Offering with New Release of the START Memory System
Virage Logic Corporation has broadened its Silicon Aware IP product portfolio with a new release of the Self-Test and Repair (STAR) Memory System. Introduced in 2001 and successfully used by over 100 companies, this new release adds capabilities to address the challenges of advanced design and process technologies. A dashboard of user-selectable options enables tradeoffs between test time, area, and state-of-the-art diagnostics for optimal design complexity management.
This release also expands the STAR Memory System's capabilities to address process challenges with a new product option called START Yield Accelerator, created to boost silicon yield and accelerate time-to-volume. The STAR Yield Accelerator bridges the design and manufacturing disciplines to enable automated test vector generation, silicon analysis, fault isolation and classification to be used at the critical semiconductor tape-out, bring-up and volume manufacturing stages.
The company also announced that for the first time, the STAR Memory System will be open to enable licensees to use the systems' capabilities with other commercially available and internally developed embedded memories.
Already proven through preliminary engagements with several key customers at advanced process nodes, the new STAR Yield Accelerator addresses the requirements of integrated device manufacturers (IDM), fabless and foundry customers to rapidly, cost-effectively and accurately identify, analyze, isolate and classify memory faults as designs are readied for transition from first silicon to volume manufacturing. By doing this automatically within the existing development workflow, STAR Yield Accelerator works in concert with the embedded test-and-repair infrastructure of the STAR Memory System to speed system-on-chip (SoC) time-to-volume and boost the yield percentages of good die per wafer. The STAR Memory System is proven to reduce tape-out schedules for new complex SoCs by weeks and the STAR Yield Accelerator can reduce silicon bring-up by months, reducing overall time-to-volume production. (Virage Logic also today announced new Silicon Aware memory and logic products. See related press release titled, "Virage Logic Expands Silicon Aware IP Offering with New 65nm Memory and Logic Products.")
"As process nodes advance, the risk and the costs of lost yield increases exponentially," noted Dr. Yervant Zorian, Virage Logic's vice president and chief scientist. "With our latest release of the STAR Memory System, licensees are well equipped to proceed with speed and confidence through the critical design and manufacturing stages, while optimizing the profit opportunities their products represent."
Anticipating significant demand for the yield-enhancing capabilities of the STAR Memory System, particularly among users designing at the advanced process nodes, Virage Logic has announced the opening of the STAR Memory System architecture to enable the integration of commercially and internally developed memories. As a result, users will have the flexibility to leverage the full benefits of the STAR Memory System, including the STAR Yield Accelerator's capabilities.
"The benefits of the STAR Memory System's silicon IP and STAR Yield Accelerator carry tremendous value for memory-dominant SoC designs. By providing an open interface to the STAR Memory System, we extend the value to designers regardless of whether they select to use Virage Logic memories, other commercially available or internally developed memories," said Brani Buric, vice president of product marketing and strategic foundry relationships. "Licensees will enjoy the flexibility of being able to mix memories from various sources and still be able to reap the benefits of the STAR Memory System's capabilities."
STAR Yield Accelerator consists of the STAR Verifier, STAR Vector Generator, STAR Debugger, and STAR Yield Analyzer components. Leveraging the infrastructure of the STAR Memory System, the STAR Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results. Using STAR Yield Accelerator, manufacturers can rapidly and directly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the IP vendor or SoC designers.
For SoC designers and manufacturers for whom on-chip memory may impact yield losses or time-to-volume, STAR Yield Accelerator offers capabilities far beyond conventional physical de-processing and manual analysis approaches thereby pinpointing the physical location of memory faults as well as providing guidance of root cause. Moreover, STAR Yield Accelerator protects manufacturers' sensitive process data -- and the designers' closely guarded design data -- by enabling engineers to troubleshoot yield issues in a secure and efficient manner.
Availability and Pricing
The new release of the STAR Memory System is available today with project-based pricing starting at $25,000. STAR Yield Accelerator is available today. Project-based engagements include software and services with pricing starting at $50,000.
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