CIMdata PLM Industry Summary Online Archive
10 September 2007
Product News
ARC and Cadence Offer New Low-Power Design Methodology for Demanding Mobile Applications
ARC International and Cadence Design Systems, Inc. announced a new automated Common Power Format (CPF)-enabled low-power reference design methodology (LP-RDM) has been implemented in ARChitect, ARC's patented processor configuration tool. This LP-RDM together with the Cadence® Low Power Solution ensures that ARC's new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power. See companion ARC press release dated September 10, 2007 for more details on Energy PRO.
"ARC and Cadence have been jointly developing a reference design flow based on the SI2 industry standard Common Power Format," said Michael Horne, group director, Industry Alliances at Cadence. "The new design flow represents the culmination of this effort. Using the Cadence Low Power Solution enabled by CPF, ARC has successfully employed a standard 90nm low-power standard cell library to perform netlist synthesis, verification, floorplanning, and routing of an ARC core to a TSMC 90nm target process. The result was a right-first-time test design that achieved its target power specifications."
"ARC and Cadence have worked together to make great strides in achieving the lowest power in SoC designs using ARC's configurable cores and subsystems at joint customers," said Paul Holt, vice president, product development and services at ARC International. "The result of our experiments with the new flow shows that customers using ARC's Energy PRO technology and employing the new LP-RDM based on Cadence technology will achieve power savings of up to four fold over conventional low-power flows of the past."
Energy PRO in the Encounter Low-Power Flow
The ability to custom configure a processor core or subsystem using ARChitect is a fundamental advantage provided to SoC designers of ARC-basedT chips. ARC's future products based on Energy PRO technology will extend this advantage by incorporating specific power-management features in the product. ARC will provide development tools which will recognize the power intent of the product and ensure that the hardware design achieves its optimal energy efficiency.
Cadence Low-Power Solution scripts are integrated into ARC's configuration tool in a Reference Design Flow (RDF) library. ARChitect allows the designer to implement various Energy PRO features while taking advantage of Virage Logic's Area, Speed and Power (ASAP) LogicT standard cell libraries and Ultra-Low-Power standard cell architecture. ARChitect then produces RTL containing the Energy PRO design intent for input to the Cadence Encounter® digital IC design platform - a key component of the Cadence Low-Power Solution. Using the industry standard SI2 Common Power Format, the Encounter platform provides RTL to netlist synthesis, verification, floor planning and routing for a TSMC 90nm process technology. Thus SoC designers can easily configure an Energy PRO processor and be assured that all its low-power capability automatically propagates through the entire Encounter flow to final layout.
Availability
The new low-power reference design methodology (LP-RDM) implemented in ARChitect is available now. For more information, contact ARC sales representatives or e-mail info@arc.com .
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