CIMdata PLM Industry Summary Online Archive
30 July 2007
Implementation Investments
Faraday Adopts Cadence Connectivity-Driven SiP Co-Design Capabilities
Cadence Design Systems, Inc . and Faraday Technology Corp., a leading fabless ASIC and IP company, announced that Faraday has adopted Cadence® system-in-package (SiP) digital co-design technology. This technology strengthens Faraday's substrate design capability and enables the company to provide SiP implementation capability to the market.
Today's fabless design companies are striving to shorten their design cycle times by prototyping as early as possible in the development stage. Cadence SiP digital co-design technology is seamlessly integrated with Cadence Encounter® technology to deliver compatibility with the chip design teams' IC flow, as well as provide compliance with the IC technology file.
"We needed technology that brings automation, integration, reliability and repeatability to SiP co-design, and we found that Cadence offers a total solution," said Kun-Cheng Wu, director of the Design Development Division at Faraday. "The SiP digital co-design technology streamlines the integration of multiple high-pin-count chips onto a single substrate, and helps us bring a more comprehensive ASIC service portfolio to our customers."
In addition to its value to system and package houses, the Cadence SiP co-design technology enables design service organizations and fabless ASIC companies to provide their customers with SiP-aware designs. Cadence SiP Digital Layout is a complete constraint- and rules-driven package substrate layout environment that supports all major packaging methods, including PGA, BGA, micro-BGA and chip scale, as well as flip-chip and wirebond attach methods.
"The cooperation with Faraday not only demonstrates our capability to offer SiP design solutions for the whole supply chain but also sets a milestone for Taiwan semiconductor next-generation technologies," said Willis Chang, country manager of Cadence Taiwan. "For Encounter users, the flow from chip floorplanning to chip optimization is leveraged through a co-design methodology that allows for integration across the IC and SiP design teams."
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