CIMdata PLM Industry Summary Online Archive
11 July 2007
Product News
Cadence Extends Integrated SiP Technologies Into the Latest Custom And Digital Design Flows
Cadence Design Systems, Inc . announced that Cadence® SiP (system-in-package) technology is now integrated with the latest releases of the Cadence Virtuoso® custom design and Cadence Encounter® digital IC design platforms, bringing significant new design capabilities and productivity enhancements. Coupled with other Cadence products, including the Cadence RF SiP Methodology Kit, Cadence offers a leading suite of SiP design technology. The new Cadence SiP technology offers an expert-engineering process optimized for automation, integration, reliability, and repeatability. With the advanced SiP technology, Cadence enables designers to converge diverse IC and package-assembly technologies into highly integrated products. This results in designers meeting escalating demands for small, high-performance products while keeping costs low.
"As a user of both Virtuoso and SiP, it's important to have the best integrated overall solution and flow," said Christian Caillon, engineering director, Cellular Communication Division, STMicroelectronics. "This latest SiP technology delivers new levels of integration and design productivity that we need in order to deliver leading-edge multi-chip package solutions to our customers."
To realize improvements in design productivity and design quality, today's IDM and fabless chip companies need seamless integration between their IC design environments and their SiP implementation technology. Therefore, Cadence SiP technology has been enhanced to maximize productivity and quality. It now supports the new OpenAccess-based Virtuoso platform for an RF-module design and circuit-simulation-based flow. It integrates a new post-layout parasitic extraction and back annotation flow into automatically maintained circuit-simulation test benches. The improved RF flow lets designers benefit from the new Virtuoso platform when designing SiP RF and analog modules. Benefits of the Virtuoso platform include its multi-technology IC simulation capabilities.
"This latest release of our SiP technology, and its integration with the latest Cadence Virtuoso and Encounter platforms, bring new levels of designer productivity and capability to the SiP design team," said Charlie Giorgetti, corporate vice president, product marketing at Cadence. "This integration of Virtuoso technology with the RF SiP flow allows designers to access multi-technology simulation for multi-chip designs at various system levels, including SiP, pre- and post-route parasitic extraction and back annotation into automatically maintained circuit-simulation test benches."
The new SiP digital flow includes logical co-design connectivity and authoring support, as part of the System Connectivity Manager. This isolates the front-end designer from physical-only changes, such as pin swap association. Enhanced digital SiP integration with Cadence SoC Encounter® RTL-to-GDSII system provides improved input/output planning, with staggered bondpad and radial wirebond bondpad spacing support that is commonly used for wirebond IC's. Other enhancements to this release, for both the RF and digital flows, include autobond for rapid wirebond padring evaluation, object-action and action-object use models, improved SI model-extraction accuracy for designs without reference planes, 3D die stack object swapping, extended manufacturing signoff rules, and capabilities for manufacturing accurate wirebond profiles and parasitic models.
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