CIMdata PLM Industry Summary Online Archive
27 June 2007
Product News
Synopsys Teams With UMC to Port Mixed-Signal Connectivity IP to 90- and 65-Nanometer Process Technologies
Synopsys, Inc. announced that it has teamed with UMC to port the Synopsys DesignWare® USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies. The DesignWare PHYs are highly complex, process-tuned analog interfaces used in today's high-volume, high-value consumer, computer, storage and networking SoCs. The DesignWare PHY IP provides 90- and 65-nm implementations of popular high-speed derail communications protocols, helping reduce risk, speeding time-to-market, and ensuring a more predictable path to silicon success.
The USB 2.0 nanoPHY for USB 2.0 is a mixed-signal IP core that is ideal for USB applications that require low power, small area, and PHY tunability. Combined with the DesignWare USB Device, Host and On-The-Go controllers and verification IP, Synopsys' DesignWare USB IP provides designers with an easy-to-integrate, interoperable USB IP solution that can be quickly implemented into next-generation applications.
The DesignWare PHY IP for PCIe, XAUI, and SATA, combined with the respective DesignWare digital controllers and verification IP, delivers a complete set of IP solutions for these protocols. The PHY IP offers the lowest power (30 to 50 percent lower than competitive solutions), high performance margins, and small die area. In addition, the ATE test vectors and a unique built-in diagnostic engine enable at-speed production testing of the mixed-signal PHYs. The associated DesignWare verification IP enables a quick and efficient way to verify PCI Express designs using the latest functional verification methodologies.
"Many of our customers are seeking standardized interface IP for the USB, PCIe, SATA and XAUI protocol standards," said Dr. Chingchi Yao, senior director of Customer Design Support at UMC. "Synopsys' high-value cores are poised to allow chip designers to quickly obtain and integrate critical functionality into their designs and then ramp into volume production. We are taking an aggressive position in making reduced-risk IP available for leading-edge designs and are among the first companies to have Synopsys port their newest portfolio of mixed-signal IP to 65 nanometer processes."
"Synopsys continues its track record of providing customers with integrated, high quality IP solutions that support the latest process technologies," said John Koeter, senior director of marketing for DesignWare IP at Synopsys. "By working closely with UMC on developing the DesignWare IP in UMC's 90 and 65 nanometer processes, we are working to enable our mutual customers to achieve first-pass silicon success."
Availability
The DesignWare USB 2.0 nanoPHY for UMC's 90LL, 65-nm SP, and 65LL processes are expected to be available in the second half of this year. The DesignWare PHY IP for PCI Express, XAUI and SATA implemented in UMC's 90LL and 65-nm SP technologies are expected to be available in early 2008. The DesignWare verification IP and digital controller cores for USB 2.0, PCIe and SATA are available today.
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