CIMdata PLM Industry Summary Online Archive
19 June 2007
Implementation Investments
Tensilica Enhances Reference Flow With Cadence Encounter RTL Compiler
Cadence Design Systems, Inc . and Tensilica, Inc. announced that Tensilica incorporated Cadence® Encounter® RTL Compiler with global synthesis in its CAD flow which supports both Diamond® and Xtensa® cores. Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP.
Tensilica , a member of the Cadence OpenChoice IP program, used a top-down methodology featuring its market-leading processor IP in conjunction with Encounter RTL Compiler, which performs multi-objective synthesis to create designs optimized for timing, area, and power.
Tensilica is a leading IP supplier in mobile multimedia (audio and video) and offers the broadest line of processor cores in the market today in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. All Tensilica processor cores are complete with a matching software development tool environment.
"We are excited to enable our customers with synthesis solutions from Cadence," said Chris Rowen, president and CEO at Tensilica. "What impressed us most about Encounter RTL Compiler is that it was easy to set up and use. Tensilica customers using the Encounter technology now have access to an optimal synthesis solution that provides excellent power-versus-area tradeoffs for SoC (system-on-chip) design."
With the RTL Compiler multi-objective optimization, customers can achieve significant advantages in area, speed and performance. In tests, Tensilica achieved a 10 percent increase in speed and a reduction of cell area of 5 percent. The RTL Compiler global synthesis solution improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.
"Encounter RTL Compiler plays a significant role in enabling our IP partners to improve their quality of silicon in a very competitive market," said Jan Willis, senior vice president, Industry Alliances at Cadence. "We are delighted to collaborate with Tensilica to jointly enable our customers for better quality, performance, and power consumption in their designs."
RTL Compiler with global synthesis is available in XL and GXL offerings to meet customers' design and cost objectives. This key technology is part of the Cadence Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution.
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