CIMdata PLM Industry Summary Online Archive
11 June 2007
Implementation Investments
AMI Semiconductor Successfully Tapes Out Design Using Conformal Constraint Designer for Constraint Signoff
Cadence Design Systems, Inc . announced that AMI Semiconductor has adopted Cadence® Encounter® Conformal® Constraint Designer XL as its ASIC Timing Constraint signoff tool, after using it to tape out multiple designs for production. The value of the technology is that it improves time to market by verifying and ensuring design constraint quality. It also goes the extra step of identifying and automatically generating missing constraints, cutting this phase of the constraint signoff from weeks to days.
By using the Cadence constraint designer technology for its ASIC signoff flow, AMIS is able to automate and efficiently manage constraint-design activities for optimum ASIC-design performance.
"The ability of the Encounter Constraint Designer solution to automatically identify and generate missing design constraints is of great benefit to AMIS," said Karla Reynolds, Director of CAD/Methodology group at AMIS. "We were able to quickly adopt this technology into our ASIC design flow in a few weeks and successfully taped out the design. This, combined with the excellent technical support provided by the Cadence field and R&D team, has prompted us to evaluate the Encounter Conformal Constraint Designer for our timing validation flow as well."
By using Encounter Conformal Constraint Designer as a constraint signoff tool, AMIS is able to detect issues in their customers' design constraints, provide reports on these issues, and allow customers to correct the constraints early in the design phase. Cadence has created a strong database of constraint data, increasing constraint quality and enabling industry leading constraint evaluations. The Cadence constraint designer features an innovative, new algorithm that automatically identifies missing constraints and generates templates which can be used by the designer to fill in the gaps -- a process which normally is done by hand and typically requires many iterations to complete. This capability significantly improves quality and time to market.
"The Encounter Conformal Constraint Designer XL is an advanced, automated constraint design technology which ensures constraint correctness and quality for AMIS and other Cadence customers," said Andy Lin, vice president of R&D for Formal Verification at Cadence. "As a constraint signoff tool, this technology improves SDC quality and accuracy and enables customers to shorten design time."
Encounter Conformal Constraint Designer is a key technology in the Cadence digital implementation solution and a component of the Cadence Logic Design Team Solution. It enables early logic-design signoff and automates the generation, validation, and refinement of constraints to ensure that timing constraints are valid throughout the entire design process, helping designers achieve rapid timing closure. The Encounter Conformal Constraint Designer is available in L and XL offerings to meet customers' design complexity and budget needs.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.