CIMdata PLM Industry Summary Online Archive
4 June 2007
Product News
Magma Software in TSMC Reference Flow 8.0 Qualified for 45-Nanometer Process Technology
Magma® Design Automation Inc. and Taiwan Semiconductor Manufacturing Company, Ltd. announced that Magma's Blast and TalusT design implementation software, QuartzT SSTA statistical analysis, Quartz DFM and SiliconSmart® DFM are included in TSMC Reference Flow 8.0. The Magma system addresses the design challenges and variability that emerge in 45-nanometer (nm) process geometries. Reference Flow 8.0 includes statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.
"Magma and TSMC are committed to providing designers with effective, reliable and cost-effective design and manufacturing capabilities for their critical ICs," said Kam Kittrell, general manager of Magma's Design Implementation Business Unit. "We're pleased that our software continues to be a key component of TSMC's Reference Flow."
Magma and TSMC worked closely to qualify the advanced low-power, statistical static timing analysis (SSTA) and design for manufacturability (DFM) capabilities of Magma's RTL-to-GDSII flow for TSMC's 45-nm process and Reference Flow 8.0.
"Magma provides a transparent and user-friendly flow that addresses routing, SSTA, DFM and low-power requirements, allowing designers to maximize 45 nm's potential," said Kuo Wu, deputy director of design service marketing of TSMC. "Magma's statistical characterization and analysis capabilities offer fast throughput while maintaining accuracy."
Process technologies at 45 nm double the transistor density compared to 65-nm processes, while creating new challenges that require a holistic, integrated approach to design. For improved accuracy, rule-based implementation flows have been augmented with model-based flows. Lithography effects that cause printed shapes to deviate from drawn are becoming more troublesome and lead to both systematic hot spots and parametric yield loss.
Chemical-mechanical polishing (CMP) and planarity effects contribute to manufacturing problems while random particulate defects also need to be managed. The emergence of 45-nm designs requires elaborate low-power techniques to minimize leakage currents and dynamic power dissipation throughout the entire RTL-to-GDSII design flow. In addition, inter- and intra-die variation, statistical leakage and statistical timing (SSTA) optimization must be incorporated into the flow.
About TSMC Reference Flow 8.0 Support
The release of Reference Flow 8.0 continues TSMC's tradition of providing design methodologies and recommended tools to enable silicon success in advanced process technologies. This design support ecosystem lowers the risk of migrating to 45-nm technology. The following Magma products are included in Reference Flow 8.0:
Blast CreateT, Blast Fusion®, Talus Design, Talus Vortex - Intelligent Timing, Area and Power Tradeoff
Magma provides a complete RTL-to-GDSII flow within a single executable file. Blast Create and Talus Design are RTL-to-placed-gates systems that logic designers use to synthesize, visualize, evaluate and improve RTL code quality, design constraints, testability requirements and floorplan. Talus Design integrates fast, full-featured, high-capacity predictable synthesis capabilities, full and incremental static timing analysis and power analysis. Blast Fusion and Talus Vortex are physical design solutions that include optimization, place and route, useful skew clock generation, floorplanning and power planning, RC extraction and a single, built-in incremental timing analyzer. Based on Magma's unified data model, this software accurately predicts final timing prior to detailed placement, eliminates timing closure iterations and enables rapid design closure while taking into account new nanometer design challenges such as on-chip variation (OCV). Talus Vortex supports TSMC's 45-nm routing rules and parasitic technology files.
Blast PowerT, Blast RailT, Talus Power, Quartz Rail - Advanced Power Management & Power Sign-off
In the TSMC Reference Flow 8.0, designers have a comprehensive RTL-to-GDSII solution for power optimization and management. Multiple power-saving design strategies have been implemented to achieve the maximum power reduction. In this system, low-power analysis and optimization engines are integrated with - and applied throughout - the entire RTL-to-GDSII flow. Talus Power supports advanced new techniques including native multi-Vt, automated multi-voltage designs, adaptive voltage scaling using concurrent multicorner optimization and multi-Vdd, and physical implementation that meets TSMC 45-nm dynamic and leakage power requirements.
With Quartz Rail, power analysis begins with RTL and continues through sign-off to ensure power integrity. Capabilities include automated power grid synthesis, static and dynamic IR-drop analysis, and induced delays and decoupling capacitor insertion to avoid voltage-peak drops. Magma's methodology also supports insertion and sizing of different types of power switches such as coarse-grain distributed and global header/footer switches and fine-grain footer switches.
Magma's low-power solution will implement the Unified Power Format (UPF) standards, and supports the UPF design power intent through Talus Power and Quartz Rail.
SiliconSmart DFM - Advanced Statistical Characterization
Due to the increasing number of variables introduced by statistical characterization, especially intra-cell characterization where there is one variable per transistor, characterization tools must provide higher performance and faster throughput. SiliconSmart DFM is the next-generation high-performance statistical characterization engine which offers a fast and accurate solution for performing statistical timing and power characterization while producing all industry-standard statistical models, in addition to Magma's proprietary statistical models, to drive Magma's Quartz SSTA.
Quartz SSTA - Managing Process Variation
At 45 nm, the traditional use of multiple process corners and design margins to combat process variation significantly compromises performance and leads to pessimistic designs. To help customers reduce the time and effort required to close timing and ensure robust designs, TSMC Reference Flow 8.0 includes Magma's Quartz SSTA. Quartz SSTA allows designers to manage process variation throughout the design flow by identifying and fixing critical paths that are sensitive to process variation. It includes support for advanced timing models such as composite current source (CCS), inter- and intra-cell variation and statistical leakage and optimization. The result is a more robust design with improved yield across the full process window and environmental conditions.
Quartz RC and Quartz Time - Accurate Sign-off Tools for Extraction and Timing
Quartz RC and Quartz Time expand Blast Fusion and Talus with a self-contained IC implementation and sign-off system for extraction, timing and noise. Developed to address customers' needs for faster design flows at advanced geometries, this Sign-off-in-the-LoopT technology eliminates external sign-off iterations and delivers correct-by-construction results, reducing sign-off to a mere checklist activity.
Quartz RC is a sign-off-quality parasitic extraction product that delivers accuracy closely correlated to QuickCap®, the acknowledged industry gold standard for parasitic extraction. Quartz RC is a full-chip extractor that can be accessed within the Blast Fusion and Talus flow or can be used as a standalone system by ASIC designers via industry-standard LEF/DEF (Library Exchange Format/Design Exchange Format) input.
Quartz Time provides accurate timing and noise analysis and sign-off. Quartz Time was designed to address the complex timing problems created by nanometer processes. Quartz Time also provides advanced timing capabilities, such as concurrent multimode and multicorner support, current source model support, as well as support for multi-voltage design and timing-impact analysis of voltage-drop-induced delay.
Blast Yield TX, Talus DFM, Quartz DFM - Improving Yields, Reducing Costs
Magma addresses design for manufacturability within the implementation flow, eliminating costly iterations associated with post-layout DFM fixing. Magma's DFM solution combines both rule- and model-based analysis, providing silicon accuracy without incurring large run-time penalties. DFM hot spots are eliminated without introducing DRC violations or affecting critical timing. Blast Yield TX and Quartz DFM are qualified by TSMC as providing foundry-accurate DFM solutions to the designer's desktop. Blast Yield TX integrates the TSMC virtual chemical-mechanical polishing (VCMP) simulator, TSMC -correlated critical-area analysis (CAA) and the layout pattern check (LPC) capabilities of Quartz DRC into the Magma Blast Fusion flow. With Blast Yield TX and Quartz DFM, designers have a complete DFM solution for minimizing both random and systematic yield loss.
New for TSMC Reference Flow 8.0 are improvements to the critical-area analysis and optimization which combine wire spreading, wire widening, redundant via insertion and via extensions into a single user-executable step. The VCMP flow utilizes a C-API for improved efficiency, providing advanced dummy metal fill for CMP hot-spot fixing. VCMP-aware parasitic extraction is available through Quartz RC and QuickCap® NX, providing silicon-accurate delay and leakage analysis. In addition, Quartz DFM can be used to identify and automatically fix LPC routing hot spots and can output litho contours to generate a lithography-aware SPICE netlist.
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