CIMdata PLM Industry Summary Online Archive
5 June 2007
Implementation Investments
Realtek Achieves Low-power Functional Closure Using Cadence Logic Design Team Solution
Cadence Design Systems, Inc. announced that Realtek Semiconductor Corporation has completed an aggressive low-power design using the Cadence® Logic Design Team Solution. Realtek is a leading Taiwan IC design house offering a comprehensive range of communication network, computer peripheral, and multimedia ICs.
"The Cadence Logic Design Team Solution does what it promises by providing the ability to analyze power management techniques and trade-offs early in the design process, ensuring the best possible power profile for the design," said Jessy Chen, Realtek's vice president and spokesman. "This approach helped our logic designers maintain high productivity levels by automating what normally is a tedious, manual effort. We are now planning to adopt the Logic Design Team Solution for our next-generation design."
With the Cadence Incisive® Design Team Manager and Incisive Design Team Simulator, logic design teams at Realtek were able to verify and simulate power shut-off logic at a very early stage in the design, ensuring that their power management logic would function properly before implementation. Early verification not only reduces risk of functional failure, but also helps ensure a productive and predictable design schedule.
"Given that 80% of the chip power gets locked in at the front end design phase, designing with power in mind becomes an imperative consideration for logic designers," said Nimish Modi, corporate vice president of Front-End Design at Cadence. "The Cadence Logic Design Team solution enables companies such as Realtek to make optimal power, timing and area tradeoffs very early in the design cycle and expediting functional closure, thereby greatly enhancing schedule predictability and improving team productivity."
The Cadence Logic Design Team Solution offers an integrated design with power approach that leverages the Si2 industry standard Common Power Format (CPF) with power-shutoff verification. The Logic Design Team Solution leverages the same CPF information used throughout the Cadence Low-Power Solution. This allows fast, accurate "what-if" analysis of various power management techniques early in the design process, ensuring high-quality power optimization and validation, while ensuring a complete power-aware flow. This flow provides simulation, power control verification, global synthesis, power-aware testing, implementation and sign-off verification, and an automated verification management process from planning to closure.
The Cadence Logic Design Team Solution
The Cadence Logic Design Team Solution allows concurrent RTL design, enabling schedule predictability. This solution equips logic design teams with elements from verification and power management to test and physical design, plus plan-to-closure management and logical signoff solution, in an integrated, holistic and concurrent approach using the Cadence Encounter® digital IC design and Incisive® functional verification platforms. It represents another deliverable in the overall Cadence segmentation strategy, offering tailored solutions for specific types of engineering teams.
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