CIMdata PLM Industry Summary Online Archive
29 May 2007
Product News
Cadence Improves Logic Designer Productivity Through Enhanced Design-With-Verification Flow
Cadence Design Systems, Inc . announced enhancements to the "design with verification" component of its Cadence® Logic Design Team Solution, resulting in significant productivity improvements for logic designers. The new capabilities reduce key verification bottlenecks, which have prevented the effective use of assertion-based verification early in the development process.
Logic designers working on assertion-based verification can now realize up to 50 times speedup and capacity improvements in SystemVerilog Assertion and Property Specification Language based formal analysis. They can realize up to 100,000 times performance increase in simulation with a single environment for Cadence Incisive® simulators and Xtreme series systems. This environment is enabled by an expansion of an innovative and unique "hot swap" capability which now allows designers to easily move, within seconds, back and forth between a leading commercial simulation tool and the Incisive Xtreme® III accelerator/emulator. Environment creation and set-up can be accomplished in as little as one tenth of the previous time with a new line of assertion-based verification IP products.
"I brought up the verification environment in just 15 minutes," said Sang Tran, Manager VLSI Technology at Newport Media, Inc. "I can say confidently that Cadence's AHB verification IP saved me several weeks, at a minimum."
An integrated assertion-based verification flow is at the heart of the "design with verification" component, leveraging a common SystemVerilog language front end, common commands, and a unified debug environment that makes the methodology and solution easy to adopt and deploy specifically by logic designers. In this flow, once the logic designers have checked their assertions using Incisive Formal Verifier, the Incisive Design Team Simulator and Xtreme Accelerator/emulator can be used to verify all assertions dynamically. The simulation is driven by either directed tests or an automated SystemVerilog testbench using an implementation of the Cadence Incisive Plan-to-Closure Methodology tailored for logic design teams.
"We are very pleased with the performance gains in the latest release of Incisive Formal Verifier," said Craig Verba, staff engineer at QLogic Corp. "When we make RTL changes and re-run Incisive Formal Verifier on one of our designs, we now have results in 40 minutes rather than three hours, which greatly increases our productivity."
"Logic design teams are asked to create increasingly sophisticated products in shrinking geometries while meeting a growing range of design objectives, such as correct reusable functionality and adequate testability," said Michal Siwinski, product marketing group director at Cadence Design Systems, Inc. "This new verification-based component enables logic designers to move from simple simulations with hand-written tests to a more efficient mix of assertions, acceleration, formal analysis and sophisticated testbenches tuned to the needs of design teams."
The Cadence Logic Design Team Solution
The Cadence Logic Design Team Solution integrates technology from the Cadence Incisive functional verification and Encounter® digital IC design platforms. It represents another deliverable in Cadence's overall segmentation strategy, offering tailored solutions for specific types of engineering teams. The Logic Design Team Solution will be featured at the Design Automation Conference (DAC) in San Diego, California, June 4-8, 2007.
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