CIMdata PLM Industry Summary Online Archive
15 May 2007
Events News
44th Design Automation Conference Announces Third Integrated Design Systems Workshop
The Design Automation Conference (DAC) announced it will offer an Integrated Design Systems Workshop on Monday, June 4, 2007. Titled "Models for Design and Manufacturing - How Modeling Challenges are Touching Every Aspect of IC Design," the third Integrated Design Systems Workshop will bring together experts in important modeling areas, such as: delay calculation, statistical timing, low power, DFM, yield, IP blocks and pcells.
Speakers will examine the necessity for model-based design and its impact on design tools and flows, as well as business implications and anticipated interactions between foundries, fabless design and EDA. Participants will then discuss significant research, development and cooperation across the industry, and debate whether it is sufficient and timely enough to meet the needs of coming technology nodes.
"As models increasingly are being used to represent everything in modern chip design flows -- from the system-level analysis through foundry process variation -- this workshop will provide valuable information and discussion for the industry," said Sumit DasGupta, senior vice president of Si2, one of the workshop's organizers. "We are pleased to offer this workshop again this year and look forward to the discussion of these challenges and their solutions in integrated design systems."
The Third Integrated Design Systems Workshop will be held on Monday, June 4, 2007 from 12 to 5 p.m. in Room 6A at DAC at the San Diego Convention Center in San Diego. Registration is $50 for ACM/IEEE members and $75 for non members, and includes lunch. For more details, contact Bill Bayer at 512-342-2244 ext. 304 or via email at bayer@si2.org . To register for the workshop, visit the DAC Web site: http://www.dac.com/ .
Third Integrated Design Systems Workshop Agenda:
1. Modeling for Power Minimization
Gary Delp - LSI Logic Corp., Rochester, MN
David Hathaway - IBM Corp., Essex Junction, VT
2. Modeling for Timing
Bob Kezer - Intel Corp., Mont Vernon, VT
Rob Aitken - ARM Ltd, Sunnyvale, CA
3. Modeling for Design Reuse
Chris Rowen - Tensilica Inc., Santa Clara, CA
James Spoto - Independent Consultant, Irvine, CA
4. Modeling for DFM/DFY
Walter Ng - Chartered Semiconductor Manufacturing, Milpitas, CA
Andrew B. Kahng - Blaze DFM, Inc., Sunnyvale, CA
5. Panel Discussion: All speakers
Moderator: Chandu Visweswariah - IBM Corp., Yorktown Heights, NY
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