CIMdata PLM Industry Summary Online Archive
8 January 2007
Implementation Investments
Apache Selected by STMicroelectronics to Address the Upcoming 45nm Design Challenges
Apache Design Solutions announced that STMicroelectronics, one of the world's largest semiconductor manufacturers, has selected Apache to jointly address the anticipated 45nm physical design challenges. The ST-Apache co-operation, codenamed STAP-45, will focus on all areas of silicon integrity, including low power, noise, timing, thermal, reliability and chip-package from 90nm to 45nm.
By collaborating with an EDA partner, ST plans to address the upcoming design challenges such as leakage vs. performance trade-off and on-chip variation (OCV) and timing convergence, as well as cost management through reduction of excessive margin, improvement of time-to-market, and avoidance of potential yield loss. Through STAP-45, ST will have early access to Apache's advanced technologies for silicon integrity platform, along with existing products such as RedHawk-EV with FAO, RedHawk-LP, PsiWinder, and Sahara-PTE. In addition, ST will provide Apache with valuable technical expertise on 45nm design processes.
"As we move towards the 45nm design process, forging partnerships with advanced EDA solution providers is a critical component in managing the anticipated challenges. We selected Apache as our partner for power and noise integrity as they have continuously demonstrated expertise and technical vision in this very important and difficult area," said Philippe Magarshack, Group Vice President, Central CAD and Design Solutions general manager at STMicroelectronics. "By collaborating with Apache, we expect to gain early exposure to new silicon integrity issues which will help reduce our potential risk for the first 45nm production design."
"ST is leading the pack in the move towards 45nm and we are excited to partner with them in meeting the upcoming design challenges," said Andrew Yang, CEO of Apache. "We look forward to the technical collaboration with ST and gaining their insight to further develop new solutions in our silicon integrity platform."
About Apache's Silicon Integrity Platform
Apache's Silicon Integrity Platform (ASIP) is a fully integrated physical design analysis, debugging, and optimization platform that considers the impact of all noise sources associated with advanced nanometer designs. ASIP considers concurrent and interdependent effects of advanced nanometer phenomena such as dynamic power, leakage, crosstalk, package/system IO, temperature, and substrate noise on silicon behavior to ensure first-silicon tapeout success. This vendor-neutral platform enables designers to adopt any industry-standard physical design flow, while providing a unified environment of extraction, characterization, simulation, and optimization for design analysis and optimization. ASIP delivers transistor-level accuracy with cell-based capacity and performance to address today's toughest design challenges. ASIP addresses the following critical aspects of silicon integrity signoff:
RedHawk-EV with FAO
A full-chip Vectorless Dynamic power analysis and optimization solution addressing dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and IO, as well as effects of on-chip inductance, package RLC, and decoupling capacitance. RedHawk with FAO automatically repairs sources of supply noise and optimizes designs to minimize power and leakage, while maintaining integrity.
RedHawk-LP
A dynamic power integrity solution for low-power and leakage management designs utilizing advanced techniques such as MTCMOS, multi-Vth, multiple voltage domains, and active-biasing. RedHawk-LP provides transient ramp-up (power-up) simulation for accurate performance vs. leakage optimization, as well as full-chip mixed-mode analysis.
PsiWinder
A clock network integrity and critical path timing sign-off solution that considers the concurrent and interdependent effects of signal integrity (crosstalk noise) and power integrity (dynamic voltage drop and ground bounce) on clock network and critical path timing. PsiWinder delivers Spice-level accuracy within a cell-based flow, enabling designers to gain a much more realistic view of clock jittering and skew, as well as the setup and hold time violations in the critical paths.
Sahara-PTE
Industry's first fully integrated power-thermal-electrical analysis and debugging solution for SoC designs with built-in power/thermal/noise library, an incremental RLC extraction for power, noise, and temperature, and tightly coupled high-capacity, high-performance power-thermal-electrical analysis engine. Sahara-PTE enables designers to analyze the impact of temperature on leakage, timing, voltage-drop, and reliability.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.