CIMdata PLM Industry Summary Online Archive
16 April 2007
Product News
Magma and Mentor Graphics Demonstrate Interoperability of Unified-Power-Format-Compliant Implementation and Verification Flow for Low-Power Nanometer Designs
Magma® Design Automation Inc. and Mentor® Graphics Corporation announced the successful implementation and verification of a design in which low-power requirements were specified in the Unified Power Format (UPF). Based on Magma's TalusT IC implementation platform and Mentor Graphics' QuestaT verification platform, the flow has been shown to reduce turnaround time for advanced low-power nanometer (nm) integrated circuits. It is the first complete flow to support the new standard. This interoperable, UPF-compliant implementation and verification flow will be showcased at the conclusion of Accellera's Low Power Workshop at the Design, Automation and Test in Europe conference in Nice.
UPF provides a single low-power description that can be used in the design and verification process and fosters tool interoperability. Without the single low-power description, each step of the design process would need to rely on the error-prone and cumbersome process of translating multiple formats and proprietary commands where the power intent could easily deviate from each other. Now design engineers using Magma's Talus IC implementation system and the verification engineer using Mentor Graphics' Questa verification environment can use the same low-power description.
The availability of the UPF standard has permitted Magma and Mentor Graphics to validate an interoperable multi-vendor low-power flow that goes from RTL through gate level to GDSII using low-power design intent such as multiple power domains, automatic insertion of level-shifters for signals that cross the voltage power domains and routing the power signals to the corresponding power supplies. The RTL design can now be synthesized to produce not only the gate-level design but the corresponding gate-level UPF file that is verification ready. The gate-level design information can then be used to implement the power-aware floorplan and to complete placement and routing of the design.
"The results of our work with Mentor Graphics establishes that the production-proven Talus IC implementation platform supports UPF," said Kam Kittrell, general manager of the Design Implementation Business Unit at Magma. "We're pleased to be working with leading EDA vendors to offer mutual customers complete low-power design flows that improve turnaround time and eliminate potential sources of errors. Our customers that develop wireless and handheld consumer devices will benefit from this cooperation."
"UPF is Accellera's answer to the design community challenge for a fast, open and inclusive low power design standard. Today, we are proudly demonstrating a multi-vendor RTL to GDSII low power flow based on UPF," said Robert Hum, vice president and general manager of Mentor Graphics' Design Verification and Test Division. "Design portability and the ability to create flows around best-in-class solutions such as Mentor Graphics' Questa Verification Platform and Magma's Talus IC Implementation Platform deliver the value that comes from open standards such as UPF."
Magma and Mentor will be demonstrating this flow on Tuesday, April 17 from noon to 3 p.m. at the conclusion of the Accellera Low Power Workshop at DATE. For details on the location and to register for the event, please visit http://www.accellera.org .
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