CIMdata PLM Industry Summary Online Archive
26 March 2007
Product News
Cadence Global Route Environment Technology Sets New Standards For PCB Design
Cadence Design Systems, Inc . announced the Global Route Environment technology for Cadence® Allegro® PCB design. This technology combines a graphical interconnect flow-planning architecture and a hierarchically-aware global routing engine to provide PCB designers with an automated, intelligent planning and routing environment. As the first solution of its kind to bring intelligent automation where no automation was previously available, Global Route Environment technology represents a significant leap forward and establishes a new PCB design paradigm.
Prior to this technology, PCB designers spent weeks or months manually routing complex, high-speed designs with many interconnected buses and multiple high pin-count devices. This resulted in prolonged and unpredictable design-cycle time, impacting project schedules and budgets. Cadence worked with several early adopter partners to help define the problem as well as drive and validate this unique solution.
"As a leading contributor to the development of the Cadence Global Route Environment technology, Motorola is pleased to be one of the first adopters of this next generation platform for printed circuit routing," said Jeff Underwood, principal staff printed circuit designer, Motorola. "By utilizing this new, enhanced routing environment, Motorola is enabling our engineers and designers to more accurately convey design intent, throughout the entire routing design process."
PCB designers have long sought a PCB environment that comprehends the global nature of the design environment that captures their design intent, provides decision feedback, and then intelligently and automatically performs design tasks adhering to their design intent. The new Global Route Environment technology offers exactly that. With the graphical interconnect flow planning architecture, it enables designers to create and define an intelligent abstraction of critical interfaces and capture interconnect design intent. This environment also leverages the global routing engine that allows designers to combine their knowledge and design intent with a hierarchical view of the design to plan the best interconnect solution possible.
"We are confident that the new Cadence interconnect flow within the Global Route Environment technology can significantly reduce redundancies in today's routing processes," said Jim Tafoya, PCB design technical manager, Sun Microsystems. "This is a ground-breaking effort and reinforces the commitment by Cadence to its PCB technology development cycle."
"Our early adopter customers have been critical in helping us understand product design requirements and then validate our unique solution," said Charlie Giorgetti, corporate vice president, Product Marketing, Cadence. "The Global Route Environment technology for Allegro PCB design helps customers quickly solve the interconnect challenges that previously would have taken weeks or even months of laborious work, threatening project schedules and budgets."
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