CIMdata PLM Industry Summary Online Archive
11 March 2007
Implementation Investments
Cadence Digital IC Design Platform Enables Global Unichip to Complete Taiwan's First 65-NM Chip Design
Cadence Design Systems, Inc . said Global Unichip Corporation, a leading system-on-chip (SoC) design foundry, is the first Taiwan-based design company to complete a successful tapeout of a 65-nanometer device. The success of this 65-nanometer tapeout further strengthened GUC's advanced technology capabilities to serve the top tier customers worldwide. GUC used the Cadence® Low-Power Solution and SoC EncounterT GXL RTL-to-GDSII system to achieve the tapeout.
"Targeting a 65-nanometer process technology is the state-of-the-art in semiconductor design," said Jim Lai, president and COO of GUC. "Success requires a tightly integrated design environment and an automated low-power design methodology. With comprehensive know-how of advanced technology designs, GUC used the combination of the Cadence Low-Power Solution and Encounter platform to build this low power design with over ten-million gates and implement it within seven weeks, which in turn helps GUC's customer to achieve a significant time-to-market advantage."
The GUC tapeout involved a customer design that is slated to move into production. GUC designed the chip using the Cadence SoC Encounter system, Encounter® Conformal® technology, and CeltIC® SI-aware nanometer delay calculator. GUC achieved higher quality of results using the design-for-yield features and design-for-manufacturing capabilities of SoC Encounter GXL, including virtual CMP and critical area analysis tools.
"We congratulate GUC on this achievement," said Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. "GUC has clearly demonstrated a leading-edge design and implementation capability that targets advanced processes with state-of-the-art, low-power design techniques, and we are honored to have been part of it."
Many of the tools used by GUC in this design are also part of the Cadence Logic Design Team Solution, which helps logic design teams improve schedule predictability through plan-to-closure management and logical signoff-in an integrated and holistic approach covering both design and verification. It represents another deliverable in Cadence's overall segmentation strategy, offering tailored solutions for specific types of engineering teams.
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