CIMdata PLM Industry Summary Online Archive
15 December 2005
Events News
Sequence Low-Power Design Seminar Attracts Top Japanese Electronics Companies; 29 Major Japanese Consumer Electronics Companies Attend Event Co-Sponsored By CoWare, Forte, HP
A recent seminar in Tokyo on low-power design issues and strategies sponsored by Sequence Design , CoWare, Forte Design Systems, and HP attracted chip designers from 29 major Japanese electronics companies, racing to solve major problems affecting chip design for consumer, mobile, and highly integrated devices. The seminar focused on four areas: predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design.
Keynote speaker Professor Takayasu Sakurai, Center for Collaborative Research, University of Tokyo, stated that power issues are becoming a real threat to the continued advance of Moore's Law. Leakage power in particular, he said, will rise dramatically in the next decade as power supplies shrink and can represent nearly one-half of power consumption in 90nm designs. He examined a number of steps being developed to control leakage, including power gating of designs, MTCMOS (Multi-Threshold CMOS) and other advanced process technologies, and several "power-aware" architectures under development in Japan.
Cradle Technologies' Amjad Qureshi, director of hardware engineering, described his experience developing a low-power design flow for a 0.13 micron, multi-million gate CT3600 MDSP (Multi-Core DSP) product with 24 processing cores. He recommends tackling power issues as early in the design cycle as possible and cited his company's use of Sequence's PowerTheater to architect the RTL code, resulting in a 30 percent reduction in power consumption. Cradle, a fabless semiconductor company providing MDSPs for video and imaging systems, is a leader in the fast-growth security and surveillance industry and prides itself on achieving low power consumption across its entire product family.
NEC Electronics' Kotaro Hachiya delivered a talk on power-noise verification and NEC Electronics' experience using Sequence's CoolTime for dynamic power grid analysis.
"Companies attending this seminar are in the three hottest semiconductor markets today: consumer, mobile, and high integration," said Sequence president and CEO, Vic Kulkarni. "Consumer applications are driven by cost, so they must produce the lowest cost, lowest power package possible. Mobile applications are driven by battery life, so power consumption must be reduced as much as possible. And high-integration devices in communications, computing, and networking are burning up from their own heat so they must look for ways to scale down power consumption. Semiconductor companies are investing heavily in these markets and are looking for partners that can help them manage power because it is critical to their success. The record attendance at this seminar proves just how important power is becoming in semiconductor design."
In addition to real-world case studies from invited speakers, the sponsors presented advances in EDA software and hardware specific to low-power design: Sequence addressed physical power optimization and power-grid integrity; Forte covered a power-driven methodology for ESL-to-netlist design flows; and CoWare discussed issues relating to ESL power management.
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