CIMdata PLM Industry Summary Online Archive
9 November 2005
Product News
UMC Brings Comprehensive Reference Design Flow to 90nm SoC Designers
UMC , a leading semiconductor foundry, announced the availability of a comprehensive reference flow for 90nm system-on-chip (SoC) designs. The silicon-verified, RTL-to-GDSII flow is based upon the foundry's proven 0.13um low-power design package ( http://www.umc.com/English/news/20050927.asp as announced in September), and incorporates timing closure, signal integrity, and power closure features to help SoC designers overcome 90nm design-related challenges. Moreover, the added dimension of the latest design for manufacturing (DFM) rules, applied within the reference flow, provides designers with new capabilities to achieve accurate, first-time-right designs and shortened time-to-market.
Ken Liou, director of the IP and Design Support Division at UMC, said, "SoC designers today require proven design support solutions to help them overcome the challenges of 90nm and below technologies. The availability of our newest, comprehensive reference flow promises to help our customers navigate the most seamless path to 90nm silicon success by providing a feature-rich solution that is supported by the latest EDA tools and DFM methodologies."
The design flow focuses on improving DFM issues by applying DFM-aware technology files at strategic areas of the flow. DFM rules and technology data are incorporated into libraries in both front-end and back-end views; thus, the entire design flow has taken DFM into consideration.
To validate the 90nm RTL-to-GDSII flow, UMC utilized its 0.13um LEON2 CPU based technology demonstrator as a reference design to implement a top-down solution. Design for test (DFT) and design for diagnosis (DFD) elements are featured to ensure design accuracy. The reference flow is available now for download at http://www.umc.com .
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