CIMdata PLM Industry Summary Online Archive
9 November 2005
Implementation Investments
Alliance Semiconductor Selects Denali Verification IP for Design and Verification of Its Products
Denali Software's PureSpecT verification intellectual property (IP) has been selected by Alliance Semiconductor Communications, Inc., for the design and verification of its products.
Alliance Semiconductor is a worldwide provider of high-value memory, mixed-signal and system solution products for the communications, computing, consumer and industrial markets. Its engineers are using PureSpec at the pre-silicon stage of verification to model and simulate interactions with other devices across industry standard interfaces. PureSpec enables Alliance Semiconductor to ensure correct and optimal design of its chip interfaces, ultimately increasing verification productivity and overall product quality.
"Alliance Semiconductor is noted for its broad portfolio of innovative solutions enabled by a leading-edge design and verification environment," says Vic Juneja, Denali's product marketing manager. "We are pleased that it selected PureSpec for its design and verification needs, and are committed to its continued success."
Adds Paritosh Kulkarni, director of ASIC Engineering for Alliance Semiconductor: "PureSpec is the most widely used and highly regarded verification solution, an important consideration for us because functional verification of our chip designs plays a crucial role in supporting our accelerated design schedule. Denali has a product well architected to support our directed and random testing. We are now leveraging that same product architecture to address the functional verification of industry standard interfaces in our chips."
PureSpec verification IP is a widely used product for verifying functionality, compliance and interoperability of standard interfaces at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the host and one or multiple devices. Composite configurations by port and function are also supported.
PureSpec additionally provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to specifications.
The highly integrated nature of PureSpec model behavior and its data generation engine enables a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, accelerating the verification task and productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design.
PureSpec supports a number of standard interfaces, including: PCI Express, Advanced Switching Interconnect (ASI), AMBA, USB, Ethernet, Serial ATA, and CE-ATA.
PureSpec is available for evaluation at: http://www.denali.com/purespec .
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