CIMdata PLM Industry Summary Online Archive

7 November 2005

Implementation Investments

Kawasaki Micro Maximizes Delay Test Coverage with Latest Cadence Technology

Cadence Design Systems, Inc. announced that Kawasaki Microelectronics, Inc. (KME) has selected Cadence® Encounter® True-Time technology, the industry's first delay test ATPG that uses design timing to automatically generate faster-than-at-speed delay tests. Cadence also introduced two key enhancements to its delay test technology, True-Time for bridges and True-Time through RAMs.

Delay defects in nanometer-scale designs significantly slow interconnect timing transitions, which makes delay testing critically important. Traditional and existing at-speed delay testing solutions are limited in their ability to detect small delay defects, resulting in high test escapes, and system and field failures. Encounter True-Time delay test includes an on-board timing engine, which automatically generates faster-than-at-speed delay tests to detect small delay defects efficiently and deterministically, thereby minimizing test escapes.

"Effective transition fault ATPG testing is a key requirement to detect delay defects in nanometer designs-a problem that will only get worse at smaller process geometries," said Hiroyuki Nakamura, Manager, CAD Development Gr. 1, Kawasaki Microelectronics, Inc. "After extensive evaluation, we have chosen Encounter True-Time delay test for our flow, based on its ability to maximize test coverage by detecting the smallest delay defects, and support for on-product clock generation for path delay and transition fault tests."

Cadence's new True-Time for bridges allows users to automatically generate delay tests that target bridging fault models, a common nanometer design defect. This new technology allows multiple types of bridging fault models to be generated automatically from potential defect sites. True-Time for bridges enables users to specify potential bridging fault sites based on signal integrity or layout analysis.

Another new feature is True-Time through RAMs. This capability addresses customer requirements to generate delay tests into and through non-scannable elements, including third-party RAMs. These new features of Encounter True-Time delay test are fully compatible with Encounter Diagnostics, the industry's leading-edge yield diagnostics product.

"Our work with top semiconductor companies such as Kawasaki Microelectronics is a further endorsement of our differentiated advantage with Encounter True-Time delay test," said Sanjiv Taneja, vice president of R&D for Encounter Test at Cadence. "Detecting the smallest delay defects before system integration-and using Encounter Diagnostics to quickly identify their root cause-ensures the highest-quality, lowest-cost, highest-yielding ICs."

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