CIMdata PLM Industry Summary Online Archive
1 November 2005
Company News
Magma to Feature Integration of DFT into the RTL-to-GDSII Flow at International Test Conference
Magma® Design Automation Inc. announced that it will be participating in the International Test Conference (ITC) Nov. 6-11 in Austin, Texas. Product demonstrations of Blast DFTT will feature memory BIST capabilities for 90- and 65-nanometer (nm) designs, including self-repair and routing-friendly architecture. With this capability Blast DFT helps designers maximize yield in leading-edge process technologies. Also see demonstrations of automated interfaces to Mentor's TestKompress and LogicVision's ETCreate.
For the seventh year in a row, Magma's R. Dean Adams, Ph.D., director of product development for DFT products and renowned industry expert, will be providing new insights into the latest concepts in built-in self-test (BIST) and built-in self-repair (BISR). The one-day tutorial entitled, "Memory Test and Self-Test for Deep-Submicron Technologies" will be held at ITC on Sunday, Nov. 6 at 8:30 a.m. CDT.
"With the introduction of Blast DFT in April and our work with Mentor and LogicVision to automate the test and debug flow, Magma has significantly expanded its DFT solution," said Dwayne Burek, director of product engineering for DFT products at Magma. "We're excited to show test engineers how they can use our solution to get early visibility into how DFT affects timing, area, power and yield and how to avoid problems that might delay design closure or decrease yield in 90- and 65-nm SoCs."
At the ITC corporate presentation sessions on Wednesday, Nov. 9 at 9:30 a.m., Mr. Burek will give a presentation entitled, "Physically Aware DFT."
Physically Aware DFT
Meeting design constraints such as area, timing and power is becoming more difficult and designers are struggling to maintain predictable schedules. Integrating design-for-test (DFT) into the design flow improves predictability and eliminates iterations. The main purpose of the comprehensive DFT architecture is to provide an efficient component test, but it can also be leveraged for silicon debug, failure diagnosis, and trend analysis for yield management. By being an integral part of the RTL-to-GDSII design flow, Blast DFT utilizes all the design data, including timing and physical information to optimize test quality and test time. By providing early visibility, chip architects can accurately predict product viability and the impact of DFT. Blast DFT provides design flow flexibility and scalability and faster turnaround time. It supports both flat and hierarchical designs and can perform DFT analysis and insertion on large designs in minutes.
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