CIMdata PLM Industry Summary Online Archive
26 October 2005
Implementation Investments
Magma's Blast Create and Blast Fusion Accelerate Implementation of a 65-nm Customer Design
Magma® Design Automation Inc . announced the successful tapeout of a 65-nanometer (nm), high-density, low-power integrated circuit (IC) using Blast CreateT, Blast Fusion® and Blast Noise®. The IC, designed by next-generation SerDes vendor Aeluros, Inc., is a high-performance, analog-intensive, 5-Gbps chip that was completed in less than three months. Magma's RTL-to-GDSII flow enabled Aeluros to address 65-nm design challenges and achieve timing sign-off for both the digital logic and analog interface portions of the design within a single environment-thereby reducing the design cycle.
"We selected Magma for our first 65-nm design after achieving first-pass silicon success on a number of 0.13-micron designs," said Don Stark, vice president of engineering at Aeluros. "We needed to establish a reliable flow that could handle custom analog blocks along with standard-cell-based digital ASIC design. Magma's easy-to-use Tcl interface and automated flow allowed us quickly to repeat the entire design process every time we made a change to the RTL or constraints. This was key to helping us achieve the performance we needed without having to add engineering resources."
"Magma is committed to delivering software and methodologies that minimize the risk of migrating to 65 nm and below," said Premal Buch, general manager of the Design Implementation Business Unit at Magma. "We're pleased that Blast Create and Blast Fusion have once again been proven to address the complexities that arise in sub-nanometer design."
A combination of 65-nm process technology and ASIC and custom designed analog circuits, the design presented several potentially time-consuming challenges. The Magma software was able to improve productivity and accelerate the design cycle. The Magma Tcl interface enabled the designers to implement the entire RTL-to-GDSII flow with a single script and simplified the process of incorporating abstracts of the analog blocks into the design. With Early Silicon Performance (ESP) reports generated by Blast Create the designers could quickly and accurately predict how their RTL and constraint changes would affect timing. The Blast Noise correct-by-construction noise optimization flow enabled rapid closure of noise issues without iterations. Magma's integrated flow provided timing sign-off for both digital logic and analog circuits. This eliminated the time-consuming circuit simulation of analog-digital, mixed-signal interfaces and simplified back-end timing verification. With Blast Fusion, the designers implemented the mixed-signal IP using an ASIC flow, avoiding the complications of a custom flow. The physical design tool's powerful, automated routing capabilities quickly and efficiently routed the thousands of nets in the design.
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