CIMdata PLM Industry Summary Online Archive
3 October 2005
Product News
Toshiba Tapes Out First UniversalArray Chip with Cadence Encounter
Cadence Design Systems, Inc. announced that Toshiba Corporation and Toshiba Microelectronics Corporation successfully taped out the first UniversalArrayT (UA) chip with Cadence® Encounter® digital IC implementation. SoC Encounter® Global Physical Synthesis (GPS) helped provide a substantial decrease in turnaround time. Toshiba has already started work on its second UA ASIC Design with SoC Encounter.
Toshiba's UA is a new type of ASIC in which wafer sign-off is accomplished after the floorplan is fixed. Pursuant to wafer sign-off, mask making and place and route are processed concurrently, helping reduce total turnaround time from the design stage through manufacturing.
"With the UniversalArray SoC design platform, wafer sign-off prior to mask making is done after floorplanning-providing a key advantage for shortening turnaround time," said Takashi Yoshimori, Technology Executive SoC Design, Toshiba Corporation Semiconductor Company. "Cadence Encounter digital IC implementation and SoC Encounter GPS provided us with the silicon virtual prototyping we needed to improve the accuracy and estimation required for first sign-off."
Toshiba's UA platform shortens the process linking EDA technology to manufacturing by helping fabricate diffusion wafers during the implementation and timing verification process. Cadence Encounter RTL Compiler optimization helped Toshiba speed timing closure with signal integrity for best quality of silicon (QoS) in the design's implementation phase.
"The continuing success of our work with important customers such as Toshiba increases Encounter's popularity," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "This is another example of the Cadence Encounter platform's rapid route to complex, high-performance SoCs, while providing them with lower power consumption."
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