CIMdata PLM Industry Summary Online Archive
3 October 2005
Acquisitions
Synopsys to Acquire HPL Technologies, Inc.
Synopsys, Inc. announced it has signed a definitive agreement to acquire HPL Technologies, Inc., a supplier of yield management software and test chip solutions. The acquisition solidifies Synopsys' position as a leading EDA vendor in design for manufacturing (DFM), and the first with a comprehensive design-to-silicon flow that links directly into the semiconductor manufacturing process. Integrating HPL's yield management and test chip technologies into Synopsys' DFM portfolio will enable customers to increase productivity and improve profitability in the design and manufacture of advanced semiconductor devices. Synopsys will also broaden its DFM research and development expertise by integrating HPL's team of experienced engineers.
Under the terms of the agreement, Synopsys will acquire HPL for approximately $13 million, or $0.30 per share. The all-cash transaction, which will require HPL shareholder approval, is expected to close during Synopsys' first quarter of fiscal 2006 and is subject to customary closing conditions.
"With the addition of this critical piece of the DFM solution, Synopsys will help customers close the productivity gap and increase profits by optimizing yield and shortening design-to-manufacture time," said Anantha Sethuraman, vice president of DFM for Synopsys' Silicon Engineering Group. "Today, the typical design-to-manufacturing cycle takes 18 to 20 months. By linking directly into the fab, Synopsys can help significantly reduce the time between concept and manufacturing, and accelerate the introduction of new designs."
Synopsys' DFM solution reaches beyond the traditional boundaries of EDA by identifying and addressing manufacturing problems early in the design process, all the way from place and route through to physical verification (RET - reticle enhancement technology), mask optimization and process tuning (TCAD). By integrating HPL into its DFM solution, Synopsys will deepen its connection to the fab and obtain direct access to the yield data needed to reduce systematic defectivity.
HPL provides customizable software products, TestChip IP and patented RDOM technologies that enable customers such as integrated device manufacturers (IDMs), fabless semiconductor companies and foundries to identify and correct yield- limiting factors in their design, technology development and manufacturing processes. HPL's tools analyze parametric, bin/sort, bitmap, MES, defect and design data as well as monitor the changes made to the process recipes resulting in expedited yield learning and yield improvement.
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